Sequential data paths in logic designs often require timing adjustments in order to overcome race conditions and other timing problems. Traditionally, such timing adjustments have included the insertion of buffers, or delay circuits within a specific path for increasing the propagation time of a given signal. However, performance characteristics of known buffers have been dependent upon parameters of a process by which the buffers have been fabricated. As the operating speed Of existing logic devices increases, it is necessary to provide buffer circuits having known delays that do not vary with respect to processing parameters.
In fabricating a Field Effect Transistor (FET) device, its resulting channel length will vary in accordance with the characteristics of the process by which the FET device is fabricated. The channel length of the FET device will vary from a nominal length by a .DELTA.L in accordance with the processing results and its series on-resistance will likewise vary from a nominal resistance proportionate to .DELTA.L/(nominal gate length). For fixed values of .DELTA.L, it can be seen that the percentage of variation, i.e. (.DELTA.L)/(nominal channel length), will be much greater for short channel length devices in contrast to long channel length devices. A short channel length device characterizes a FET device having a channel length corresponding to a minimum channel length available from a given process (e.g., 0.5 .mu.m). A long channel length device characterizes a FET device having a channel length at least 1.5 times greater than the minimum channel length available from the given process (e.g., &gt;0.75 .mu.m).
If a buffer circuit employs certain channel length FETs for driving a fixed capacitive load, the buffer will exhibit a propagation delay proportional to the RC time constant associated with the series on resistance R of the output FETs and the capacitance C of the capacitive load. With the propagation delay of the buffer being dependent upon the series on-resistance of the FET, and the percentage of variation in series on-resistance with respect to processing parameters being greater for short channel length devices in contrast to long channel length devices, it follows that a buffer employing short channel length FETs will exhibit proportionately greater variations in propagation delay with respect to processing parameters than will a buffer employing long channel length FETs. Thus, a buffer employing short channel length FETs has a propagation delay greatly dependent upon the process by which it is fabricated while a buffer employing long channel length FETs provides a propagation delay that is only slightly dependent upon the process by which it is fabricated.